Methods of programming and circuitry for a programmable element

ABSTRACT

As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

TECHNICAL FIELD

[0001] The present invention relates generally to the computer memoryfield and, more specifically, to methods and circuitry concerningprogramming elements of memory devices.

BACKGROUND

[0002] The fabrication and operation of electronic circuitry on a dieoften involves allowing for voltages or electronic signals to bereceived from sources external to the die by way of terminals on the diesuch as contact pads electrically conductive areas that are relativelylarge in relation to a conductive line coupled thereto. The relativelylarge area of such pads allows them to receive voltages and signals fromnodes such as bond wires or probe tips.

[0003] Concerning Dynamic Random Access Memory (DRAM) devices, forexample, it is often desired to provide a pad that receives a voltagedesignated as “DVC₂.” In normal operation, the DVC₂ voltage is ideallyhalf of the full voltage (Vcc) under which the memory device operatesand which corresponds to a logic “1” value that may be stored in memory.The DVC₂ voltage is applied to the DRAM's digit lines, including themain digit lines as well as the complementary digit lines, beforereading from or writing to a memory cell.

[0004] Writing to a memory cell further involves transmitting at leastone command, such as a “write enable” (WE) signal, to the DRAM's controlcircuitry. It is often desirable to provide a pad configured to receivethe WE signal.

[0005] Moreover, operation of a DRAM may involve blowing an anti-fuse.Doing so may reroute a signal to or from a device other than the oneoriginally configured to be associated with that signal. For example, inthe event a defective memory cell is detected, an appropriate anti-fusemay be blown so that the relevant signals are associated with aredundant cell. Blowing an anti-fuse often involves generating enough ofa voltage difference between the opposing plates of a capacitor to breakdown the dielectric between those plates. For instance, one plate may becoupled to a voltage source, herein referred to as CGND (also known asVpop), while the other plate may be coupled to ground through atransistor. Thus, when CGND is applied to one plate and the transistorallows the other plate to be grounded for a sufficient time, a short iscreated between CGND and a node coupled to the other plate.Subsequently, the voltage of CGND is lowered and the transistor isolatesthe pathway to ground. As with the DVC₂ voltage and the WE signal, a padmay be used to provide the CGND voltages. However, to provide yetanother pad—one dedicated to this purpose—would require more die spaceand go against the desire in the industry to use as little space aspossible per die in order fabricate more die on each silicon wafer.Further, providing such a pad would require more test resources per die,which decreases the ability to test in parallel and increases test timeand cost. As a result, a pad that serves another function may be chosento transmit the CGND voltage as well. Which pad is chosen depends onseveral factors.

[0006] Two factors to be considered in choosing the pad for CGND involvethe notions that (1) blowing anti-fuses may be desired at several stagesin the process of fabricating a memory device; and (2) some contact padsmay not be available later in the process. The pad receiving DVC₂, forexample, is accessible for anti-fuse blowing that may occur during aproduction stage known as “probe.” At that stage, testing an unpackageddie may occur by applying voltages directly to the die's pads usingconductive pins from a test device. However, at some point after probe,the die is packaged. As a non-limiting example of packaging, some of thecontact pads may be bonded to wires leading to conductive fingers of alead frame. The die is then encapsulated with a protective material,with the far ends of the fingers projecting from the encapsulant. Someof the contact pads, however, may not be bonded to wires and aretherefore inaccessible after packaging. Nevertheless, additionaltesting, repairing, or reconfiguring of the die may be desirable at thisstage, known as “backend.” The DVC₂ pad is a contact pad that is notbonded to a wire and is therefore inaccessible after packaging. As aresult, one of ordinary skill in the art is encouraged to choose anotherpad to provide CGND.

[0007] A pad receiving the WE signal may be available during both probeand backend; but if a pad is accessible by a tester at backend intesting/reconfiguration modes, it may also be accessible by apost-production user during non-test/non-reconfiguration/standardoperation modes. Because it is not desirable to allow such a user toaffect CGND, the conductive path from the write pad to the anti-fusemust be regulated, such as with a transistor. However, in order toensure that sufficient voltage passes through the transistor during ananti-fuse blowing mode at backend, self-booting circuitry is included.As discussed in greater detail below, such circuitry is not foolproof,and additional delays may be introduced into the anti-fuse blowingprocess.

[0008] As a result, there is a need in the art to address the time,methods and circuitry of blowing an anti-fuse.

SUMMARY

[0009] Accordingly, exemplary embodiments of the current inventionconcern a direct connection between a die's anti-fuse and a die terminalconfigured to receive an external voltage. In a preferred embodiment,the terminal is also configured to provide voltage to another device.When a voltage is being supplied to that other device, and that voltagewould affect the ability of circuitry to properly determine the statusof the anti-fuse, preferred embodiments of the current invention isolatethe anti-fuse from such circuitry. In a more preferred embodiment,access to the terminal is eventually prevented, but access to theanti-fuse by way of a still-accessible second terminal is allowed,wherein the connection between the anti-fuse and the second terminal isregulated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 depicts an anti-fuse circuit and a latch circuit known inthe prior art.

[0011]FIG. 2 depicts an anti-fuse circuit and related circuitry known inthe prior art.

[0012]FIG. 3 depicts the voltages at various nodes of a regulationtransistor known in the prior art.

[0013]FIG. 4 depicts an exemplary embodiment of the current invention.

[0014]FIG. 5 depicts memory circuitry known in the prior art.

[0015]FIG. 6 depicts another exemplary embodiment of the currentinvention.

[0016]FIG. 7 depicts yet another exemplary embodiment of the currentinvention.

[0017]FIG. 8 depicts still another exemplary embodiment of the currentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018]FIG. 1 shows prior art circuitry 10 comprising an anti-fusecircuit 11 and a latch circuit 18. The anti-fuse circuit 11 comprises acapacitor—the anti-fuse 12—wherein one plate of the capacitor isconfigured to couple to a voltage source CGND and the other isconfigured to couple to ground through node 14 and a transistor 16.Before blowing, the dielectric between the plates of anti-fuse 12 isintact, thereby electrically isolating node 14 from CGND. In anon-limiting example of blowing the anti-fuse, CGND is established to beten volts and the gate of transistor 16 is driven for at least 2milliseconds. As a result, the dielectric between the plates ofanti-fuse 12 breaks down, and a conductive path from CGND to node 14 isestablished. Subsequently, the voltage of CGND is lowered, preferably toless than Vcc.

[0019] While CGND is high, however, there is a risk of damaging thelatch circuitry 18. In order to prevent such damage, a voltageregulation transistor 17 is electrically interposed between theanti-fuse circuit 11 and the latch circuit 18. In the prior art, thisvoltage regulation transistor 17 is turned off only during the anti-fuseblowing mode. Any other time, a voltage that is slightly less than Vccis applied to the gate of voltage regulation transistor 17 by way ofsignal FLTV (Fuse Latch Transistor Voltage). For instance, 200millivolts less than Vcc may be applied. As a result, the maximumvoltage that could be applied from the anti-fuse circuit 11 to thesource of voltage regulation transistor 17 is Vcc minus 200 millivoltsand minus the threshold voltage of voltage regulation transistor 17.Such a voltage provides enough electrical communication for reading thestate of the anti-fuse 12 using latch circuit 18 while protecting itfrom excess voltages. Prior artisans are taught to maintain this sub-Vccvoltage to the gate of voltage regulation transistor 17 at all timesother than during an anti-fuse-blowing mode. This is due at least inpart to the fact that prior art already provides other protectioncircuitry between the pad receiving the voltage and the CGND node (suchas the pass gate 42 described below) that is to be used in times otherthan the anti-fuse-blowing mode. Thus, to shut off regulation transistor17 outside of that mode would result in unnecessary redundancy.

[0020] As mentioned above, latch circuitry 18 is used to determine thestate of the anti-fuse 12. An example of such circuitry includes aninverter 20 with an input coupled to node 14 (through voltage regulationtransistor 17) and an output node OUT that drives a p-channel transistor22 and an n-channel transistor 24. The p-channel transistor 22 has asource coupled to Vcc (assumed to be 3 volts) through a current-limitingp-channel transistor 23. The drain of p-channel transistor 22 is coupledto the input of inverter 20. The n-channel transistor 24 has a sourcecoupled to ground. A second p-channel transistor 26 has its sourcecoupled to Vcc (through p-channel transistor 23) and its drain coupledto the input of inverter 20. A second n-channel transistor 28 has itsdrain coupled to the input of inverter 20 and its source coupled to thedrain of n-channel transistor 24. The gates of second n-channeltransistor 28 and second p-channel transistor 26 are coupled and drivenby a signal RDFUS that is transmitted when one desires to read whetherthe anti-fuse has been blown.

[0021] The results of such reading depend on whether the anti-fuse 12 isblown and whether CGND represents a low enough voltage. In any case, thestatus of the anti-fuse 12 is read when RDFUS represents a low voltageor “logic 0” signal. Such a signal turns on the second p-channeltransistor 26 and turns off the second n-channel transistor 28. As aresult, the transistors 26 and 28 in this state attempt to raise thevoltage of node 14 and the input of the inverter 20 to Vcc. If theanti-fuse 12 is unblown, node 14 is isolated from the low CGND voltage(and it is assumed that transistor 16 is off as well). Because the inputof inverter 20 has a high voltage, its output OUT is a low voltage or“logic 0” signal, which represents the fact that the anti-fuse isunblown. If the anti-fuse is blown, however, then there is a path fromnode 14 and the input of inverter 20 to a voltage lower than Vcc (CGND).The resulting discharge results in a low voltage or logic 0 signal inputto inverter 20. Accordingly, the output OUT of inverter 20 is a highvoltage or logic 1 signal, which represents the fact that the anti-fuseis blown. This second example assumes that CGND is low enough below Vccsuch that a logic 0 is recognized at the input of inverter 20.Typically, CGND is held at ground during modes that do not involveblowing an anti-fuse. However, if for some reason CGND is not lowenough, the input of inverter 20 may not sufficiently discharge throughthe anti-fuse 12. As a result, a logic 1 may be recognized at the inputof inverter 20, and the output OUT will be a logic 0, signifying anunblown anti-fuse when in fact the anti-fuse is blown.

[0022] Even if the low voltage RDFUS command is not given, the outputnode OUT will still reflect the status of the anti-fuse 12, and thelatch circuit 18 may suffer the same problem discussed above if the CGNDis too high at the wrong time. If RDFUS has a high voltage representinga “logic 1,” the second p-channel transistor 26 is turned off and thesecond n-channel transistor 28 is turned on. If the anti-fuse 12 isblown, the input to inverter 20 should have a low voltage. As a result,the output node OUT will have a high voltage that turns off p-channeltransistor 22 and turns on n-channel transistor 24. Thus, the input ofinverter 20 will be isolated from Vcc and grounded, thereby maintainingthe high voltage signal at OUT, which signifies a blown anti-fuse.However, if the anti-fuse is blown but CGND is too high, then there is arisk that the input node of inverter 20 may have a high enough voltagefor long enough to result in a low voltage signal at the output nodeOUT. When that voltage is applied to the gates of transistors 22 and 24,it isolates the input of inverter 20 from ground and allows the Vccsource to electrically communicate with the input of inverter 20,thereby maintaining a low voltage signal at OUT, which incorrectlysignifies an unblown anti-fuse.

[0023] Thus, regardless of the state of RDFUS, if for some reason CGNDis not low enough, the latch circuit 18 may indicate that the anti-fuse12 is unblown when in fact it is blown. This could reverse the effect ofany changes that the blown anti-fuse 12 is supposed to govern. Onereason that CGND may not be low enough is if the contact pad used tocarry the CGND voltage serves another function involving increasedvoltages. Although using one contact pad for multiple functions maycreate the potential for certain problems to arise, one of ordinaryskill in the art is nevertheless encouraged to share such resources inorder to conserve die space. For reasons discussed in the Backgroundsection, one of ordinary skill is further encouraged to share the CGNDfunction with a pad that can be accessed at backend as well as probe,such as the WE pad 38 depicted in FIG. 2. FIG. 2 shows that, in additionto transmitting the CGND voltage to anti-fuse 12, the WE pad 38 iscoupled to memory control circuitry 39. It should be noted, however,that the WE pad 38 is not directly connected to the anti-fuse 12.Rather, any signal from the WE pad 38 must first pass through the drain44, channel 45, and source 46 of a transistor identified as a pass gate42, which is part of a larger self-booting pass gate circuit 40.

[0024] Such regulation of the signal stems from another issue raised bythe fact that the WE pad may be accessed after packaging. Specifically,if a tester can transmit a high voltage during testing through a leadfinger, bond wire, and pad 38 to CGND node 52, so too can acustomer/end-user transmit a high voltage to that same destinationduring non-anti-fuse-blowing modes of operation. As described above, theresult could be that the voltage output from the anti-fuse circuit 11would indicate that the anti-fuse is unblown when, in fact, it has beenblown. This may reconfigure the die's circuitry and interfere with itsoperation. As a result, pass gate 42 is provided and is turned offduring non-fuse-blowing modes of operation in order to preventelectrical communication between pad 38 and the CGND node 52.

[0025] Only when an anti-fuse-blowing mode is desired is the gate 48 ofpass gate 42 driven. Further, the voltage required for such a modeencourages the use of capacitor 50 as illustrated in FIG. 2. Capacitor50 is coupled to both the source 46 and gate 48 of the pass gate 42.When the time comes to blow an anti-fuse, prior art teaches providingten volts at the CGND node 52 using the WE pad 38. Thus, ten volts isapplied to the WE pad 38, and the pass gate circuitry ideally operatesto transmit that voltage to the CGND node 52 in the manner describedbelow.

[0026] Regardless of the voltage applied to drain 44, the maximumvoltage that can be generated at the source 46 is equal to the voltageapplied to the gate 48 minus the threshold voltage of pass gate 42.Hence, it is desired to apply a voltage to gate 48 that is high enoughabove the voltage applied to the drain 44 so that the drain 44 voltagemay generate the same voltage at the source 46. Thus, before theanti-fuse blowing process begins, the drain 44, gate 48, and source 46are at zero volts, as illustrated in FIG. 3 at time t₀. In anticipationof the anti-fuse blowing process, three volts are applied to gate 48before a voltage is applied to the drain 44 at time t₁. At that time t₁,the voltage of the drain 44 is gradually raised from zero volts. Whenthe drain 44 reaches one volt, the gate (already at three volts) allowsthat one volt to be applied to the source 46. Given the configuration ofthe pass gate circuitry, that one volt is also applied to the capacitor50 which, in turn, causes the voltage at the gate 48 to increase to fourvolts. As a result, at a time within the range t_(X), the gate 48voltage stays higher than the drain 44 voltage, and the full voltage atthe drain 44 is applied to the source 46 and the CGND node 52.

[0027] The paragraph above describes the ideal operation of the passgate circuitry 40. In reality, however, the capacitor 50 leaks charge.As a result, the ability of the capacitor to keep the gate 48 voltageabove the drain 44 voltage decreases over time. Eventually, the gate 48voltage is lower than the drain voltage 44, as depicted in FIG. 4 aftertime t₂. Even before t₂, the source 46 voltage begins to lower, as itsmaximum may only be V_(gate)−V_(threshold)). Thus, at some point, thevoltage at the source 46 is not sufficient for a reliable anti-fuseblow. In addition, it should be appreciated that the CGND node 52 may becoupled to more than one anti-fuse 12 and that blowing multipleanti-fuses in parallel further lowers the source 46 voltage. Inpractice, the source 46 voltage is sufficient for blowing ten anti-fusesin series. Additional blows will be increasingly uncertain. As a result,after ten anti-fuse blows in series, prior art teaches carrying out a“boot-up” process, wherein the drain 44, gate 48, and source 46 aregrounded; and the voltages are increased again as described in the aboveparagraph. During probe, this boot-up process represents about 20% ofthe test time it takes to blow all fuses and repair.

[0028] At least one exemplary embodiment of the current inventionaddresses this problem by providing a direct connection between acontact pad and the CGND node, as seen in FIG. 4. Illustrated therein isan electrically continuous conductive line leading from contact pad 30to the anti-fuse 12. In this exemplary embodiment, the contact pad 30 isalso used to transmit a voltage DVC₂ for the benefit of equilibrationcircuitry 36. FIG. 5 illustrates the equilibration circuitry 36.Equilibration circuitry 36 will short digit lines D and D* in responseto a signal EQ. In further response to signal EQ, a voltage of DVC₂ isestablished at both D and D*, which is encouraged before attempting toread from or write to memory cell 34. In normal operations, DVC₂ is halfof Vcc. During certain test modes, however, DVC₂ may be higher in orderto test the margin of a sense amp 32. The contact pad 30 is used toinitially provide the DVC₂ voltage for equilibration circuitry 36;thereafter, the DVC₂ voltage is generated internally and the contact pad30 is isolated from equilibration circuitry 36 unless it is needed toprovide a different voltage for that circuitry 36, such as for margintesting.

[0029] Such differing voltages are one factor that discourages one ofordinary skill in the art from using such a pad for CGND. As mentionedabove, a high voltage at CGND in the prior art risks having the latchcircuitry 18 mistakenly indicate that a blown anti-fuse is unblown. Atleast one exemplary embodiment of the current invention addresses thisissue by countering another teaching in the art. Specifically, such anembodiment proposes turning off regulation transistor 17 during at leastone mode other than the one in which anti-fuses are blown—preferablyincluding the testing mode in which DVC₂ is raised. Thus, although node14 may reflect a logic 1 value in the event anti-fuse 12 is blown andCGND is high enough, the lack of drive to the gate of transistor 17prevents that value from being input to inverter 20 and signifying anunblown anti-fuse at the output node OUT.

[0030] Another factor that would discourage one of ordinary skill in theart from using a contact pad such as the DVC₂ pad 30 is that, sometimeafter probe and before backend, access to the DVC₂ pad 30 by externaldevices is denied. Specifically, the die undergoes the packaging processwithout a wire being bonded to that pad 30. Moreover, access to the FLTVsignal is denied as well. Accordingly, it is preferred under at leastsome of the exemplary embodiments of the current invention to maintainthe regulated connection between CGND node 52 and the WE pad 38. A greatbenefit is still realized under exemplary embodiments of this type, asit has been found that only one or two anti-fuses per die are blown atbackend, whereas probe generally involves blowing two to ten thousandanti-fuses per die, and this number should increase as density increasesin terms of devices per unit area of the die. Thus, with the directconnection eliminating the need for a self-booting pass gate circuit andthe problems related to it, the 20% of anti-fuse blowing time devoted toreboot at probe is saved.

[0031] Exemplary embodiments of this type also allow for blowing severalanti-fuses in parallel without comprising the voltage of CGND. In fact,given the direct connection to CGND, the only limitation on the voltageof CGND is the current supply from the tester.

[0032] It should be noted that in the exemplary embodiments describedabove, the regulation transistor 17 is illustrated as an n-channeltransistor. However this particular type of transistor is not relevantto all embodiments. In fact, providing a p-channel transistor forregulation transistor 17 offers certain benefits. As shown in theexemplary embodiment of FIG. 6, a p-channel regulation transistor 17 maybe driven by the same DVC₂ pad 30 used to provide CGND to node 52. Whenthe voltage of the DVC₂ pad 30 is at ground, regulation transistor 17 isturned on, and the latch circuit 18 may determine the status of theanti-fuse 12. Should the voltage of DVC₂ pad 30 increase, either due tomargin testing, an anti-fuse blowing mode, or another reason, thatvoltage will serve to further turn off the regulation transistor 17,thereby further protecting the latch circuit 18 from that very voltage.In yet another embodiment seen in FIG. 7, FLTV may still be used todrive regulation transistor 17 (provided the logic generating thatsignal is configured to accommodate a p-channel transistor rather thanan n-channel transistor), and a multiplexer 54 is used to switch betweenthe two inputs.

[0033] Further, exemplary embodiments of the current invention may beused to accommodate systems using memory, wherein the memory may includenonvolatile, static, or dynamic memory, and wherein the memory may be adiscrete device, embedded in a chip with logic, or combined with othercomponents to form a system on a chip. Further, such configurationsrepresent exemplary embodiments of the current invention themselves. Forexample, the embodiment in FIG. 8 illustrates a computer system 232,wherein a microprocessor 234 transmits address, data, and controlsignals to a memory-containing device 236 such as one including but notlimited to those described above. A system clock circuit 238 providestiming signals for the microprocessor 234.

[0034] One skilled in the art can appreciate that, although specificembodiments of this invention have been described above for purposes ofillustration, various modifications may be made without departing fromthe spirit and scope of the invention. For example, while exemplaryembodiments addressed above address directly connecting the CGND node 52to a contact pad that 30 that will not receive a wire bond by the end ofthe die packaging process, the current invention includes within itsscope exemplary embodiments that do not involve any wire bonding of thedie. For instance, at least one exemplary embodiment concernscommunicating with at most some of the die's bond pads using a ball gridarray (BGA), wherein traces leading from the balls to the pads avoid atleast one contact pad that may be used to provide a high CGND voltagefor blowing an anti-fuse at probe. Moreover, DVC₂ is not the only padthat may be used to provide the CGND voltage. For instance, at the timeof filing this application, Micron Technology is experimenting with apart that transfers data at a Double Data Rate (DDR—both on the risingand the falling edge of a clock pulse). This part uses a pad designatedas “QFC” to provide high CGND voltage for blowing an anti-fuse.Alternatively, any pad designated as a “no connect” pad could be used.Moreover, the current invention is not limited in scope to methods andcircuitry involving anti-fuses. Rather, fuses and other programmableelements are included within the scope as well. Moreover, the currentinvention includes embodiments involving any circuit device wherein afirst voltage is used in a first mode of that device and a secondvoltage is used in a second mode of that device, and the first andsecond voltages are provided to the die at a shared terminal.Accordingly, the invention is not limited except as stated in theclaims.

What is claimed is:
 1. A portion of circuitry for a circuit comprisingan anti-fuse, a first contact pad coupled to a first circuit device, asecond contact pad coupled to a second circuit device, wherein saidportion comprises a continuous electrical conductor coupled to saidfirst contact pad and said anti-fuse.
 2. The portion of circuitry inclaim 1, wherein said conductor provides a direct connection betweensaid first contact pad and said anti-fuse.
 3. The portion of circuitryin claim 2, wherein said direct connection avoids a channel of anytransistor.
 4. The portion of circuitry in claim 2, wherein said directconnection avoids a combination of a source and a drain of anyparticular transistor.
 5. The portion of circuitry in claim 2, whereinsaid conductor is coupled to said second contact pad.
 6. The portion ofcircuitry in claim 5, wherein said conductor is coupled to said secondcontact pad through a source, a channel, and a drain of a transistor. 7.Circuitry for a semiconductor die, comprising: a first circuit device; afirst electrically conductive terminal coupled to said first circuitdevice; an electrically conductive electrode that is discrete from saidcircuit device; and an electrically conductive path coupled to saidelectrically conductive electrode and said first electrically conductiveterminal, wherein said path is unregulated by a transistor.
 8. Thecircuitry in claim 7, wherein said electrically conductive electrode isa capacitor plate.
 9. The circuitry in claim 8, wherein said capacitorplate is a portion of an anti-fuse.
 10. The circuitry in claim 9,wherein said first terminal is configured to couple to at least onevoltage source external to said die.
 11. The circuitry in claim 9,wherein said first terminal is a first contact pad.
 12. A packagedcircuit, comprising: a wire; a first pad bonded to said wire; a secondpad unbonded to any wire; and a programmable element directly coupled tosaid second pad and indirectly coupled to said first pad.
 13. Thepackaged circuit in claim 12, further comprising a transistor coupled tosaid programmable element and said first pad, wherein said transistor ispositioned to regulate electrical communication between saidprogrammable element and said first pad.
 14. Circuitry for a die,comprising: a first terminal on said die and located to receive aplurality of voltage signals from at least one source external to saiddie; a second terminal on said die and located to receive a plurality ofvoltage signals from at least one source external to said die; ananti-fuse; and a node in unregulated electrical communication with saidfirst terminal and said anti-fuse, said node being in regulatedelectrical communication with said second terminal.
 15. A circuit for asemiconductor die, comprising: a first pad on said semiconductor die,wherein said first pad is configured to receive at least a firstexternal voltage; a transistor coupled to said first pad; and a secondpad coupled to said first pad through said transistor, wherein saidsecond pad is configured to receive at least a second external voltage.16. The circuit in claim 15, further comprising a programming devicecoupled to said second pad.
 17. The circuit in claim 16, wherein saidprogramming device is coupled to said first pad through said transistor.18. Memory circuitry, comprising: an equilibration circuit; a firstcontact pad coupled to said equilibration circuit; a memory controlcircuit; a second contact pad coupled to said memory control circuit; ananti-fuse circuit comprising: a voltage node coupled to said firstcontact pad, an anti-fuse coupled to said voltage node, at least onetransistor coupled between said anti-fuse and ground; a pass gatecoupled between said voltage node and said second contact pad; and acapacitor coupled to said pass gate.
 19. The memory circuitry of claim18, further comprising: a voltage regulation device coupled to saidanti-fuse circuit; and a latch circuit coupled to said voltageregulation device.
 20. Electrical communication devices for programmablecircuitry within a packaged part, wherein said part includes a latchcircuit and a bonded pad, comprising: an unbonded pad within saidpackaged part, wherein said pad is directly coupled to said programmablecircuitry; and a first transistor directly coupled to said programmablecircuitry and between said programmable circuitry and said latchcircuit.
 21. The electrical communication devices in claim 20, furthercomprising a second transistor directly coupled to said programmablecircuitry and between said programmable circuitry and said bonded pad.22. A computer system, comprising: a microprocessor; a clock circuitcoupled to said microprocessor; and a circuit device coupled to saidmicroprocessor and comprising: a programmable element, and a conductiveterminal directly coupled to said programmable element.
 23. The computersystem of claim 22, wherein said conductive terminal is electricallyisolated from said microprocessor and said clock circuit.
 24. Thecomputer system of claim 22, wherein said circuit device is a memorydevice.
 25. The computer system of claim 22, wherein said programmableelement is an anti-fuse.
 26. A voltage regulation circuit for aprogrammable element configured to receive a voltage from a node, and alatch circuit configured to read a state of said programmable element,said voltage regulation circuit comprising: a transistor configured tocouple to said latch circuit; and a first conductive path coupled tosaid transistor, wherein said first conductive path extends to said nodeand is interrupted only by said programmable element.
 27. The circuit inclaim 26, wherein said transistor is an n-channel transistor.
 28. Thecircuit in claim 26, wherein said transistor is a p-channel transistor.29. The circuit in claim 28, wherein said first conductive path iscoupled to a source of said transistor; and wherein said circuit furthercomprises a second conductive path coupled to a gate of said transistorand extending to said node.
 30. The circuit in claim 29, furthercomprising a multiplexing circuit configured to receive an input, andwherein said second conductive path is interrupted by said multiplexingcircuit.
 31. A circuit comprising: an anti-fuse; and a first contact paddirectly coupled to said anti-fuse.
 32. The circuit in claim 31, furthercomprising equilibration circuitry coupled to said first contact pad.33. The circuit in claim 31, further comprising a second contact padindirectly coupled to said anti-fuse.
 34. The circuit in claim 33,further comprising: packaging material over said first contact pad andsaid second contact pad; conductive material extending from said secondpad through said packaging material; and wherein no conductive materialextends from said first contact pad through said packaging material. 35.The circuit in claim 33, further comprising a self-booting pass gatecircuit electrically interposed between said second contact pad and saidanti-fuse.
 36. The circuit in claim 33, further comprising memory writecontrol circuitry coupled to said second contact pad.
 37. A method ofconfiguring a semiconductor die, comprising: sharing a die terminalbetween a first device on said die and a second device on said die,wherein said first device is configured to receive a voltage throughsaid die terminal; allowing unregulated electrical communication betweensaid die terminal and said second device, wherein an act of determininga status of said second device while said voltage is present at said dieterminal may result in an incorrect determination of said status; andpreventing said act of determining while said voltage is present at saiddie terminal.
 38. The method in claim 37, further comprising: includinga circuit on said die, wherein said circuit is configured to performsaid act of determining; and isolating said circuit from said seconddevice while said voltage is present.
 39. The method in claim 38,wherein said isolating act comprises: electrically interposing atransistor between said circuit and said second device; and preventingelectrical communication between said circuit and said second deviceusing said transistor.
 40. The method in claim 39, wherein said act ofpreventing electrical communication comprises turning off saidtransistor in direct response to said voltage being present at said dieterminal.
 41. The method in claim 40, wherein said sharing act comprisessharing a die terminal between an equilibration circuit and ananti-fuse, wherein said equilibration circuit is configured to receive amargin-testing voltage through said die terminal.
 42. A method ofprotecting a latch circuit from receiving a voltage from a voltagesource through an anti-fuse circuit after an anti-fuse-blowing mode ofsaid circuit, said method comprising: electrically interposing a devicebetween said latch circuit and said anti-fuse circuit, wherein saiddevice is configured to selectively block electrical communicationtherebetween; and blocking all electrical communication between saidlatch circuit and said anti-fuse circuit, wherein said blocking actoccurs outside of said anti-fuse-blowing mode and while said voltage ispresent at said anti-fuse circuit.
 43. The method in claim 42, furthercomprising refraining from interposing any device between said voltagesource and said anti-fuse that is configured to selectively blockelectrical communication therebetween.
 44. A method of regulating thevoltage transmitted through an anti-fuse to a circuit, said methodcomprising: providing a first voltage regulator between said anti-fuseand said circuit, wherein said voltage regulator is configured todiscourage electrical communication therethrough when inactivated; andinactivating said first voltage regulator when a voltage is transmittedto said anti-fuse, wherein no other voltage regulator is present betweena first source of said voltage and said anti-fuse.
 45. The method inclaim 44, further comprising inactivating said first voltage regulatorwhen a voltage is transmitted to said anti-fuse, wherein a secondvoltage regulator is present between a second source of said voltage andsaid anti-fuse, and wherein said second voltage regulator allowselectrical communication therethrough.
 46. The method in claim 45,wherein: said method further comprises at most partially activating saidfirst voltage regulator when a low voltage is transmitted to saidanti-fuse; and said act of inactivating said first voltage regulatorwhen a voltage is transmitted to said anti-fuse, wherein no othervoltage regulator is present between a first source of said voltage andsaid anti-fuse comprises: inactivating said first voltage regulator whena high voltage is transmitted.
 47. A method of providing voltage to acircuit including a first pad, a second pad, and a programmable element,and-a latch, said method comprising: allowing electrical communicationwith said programmable element through said first pad before packagingsaid circuit, wherein a conductive path from said first pad to saidelement is free of regulation by any transistor; and preventing allelectrical communication to said programmable element through said firstpad after packaging said circuit.
 48. The method in claim 47, furthercomprising preventing at most some electrical communication with saidlatch through said first pad before packaging said circuit.
 49. Themethod in claim 48, further comprising allowing electrical communicationwith said programmable element through said second pad, wherein aconductive path from said second pad to said element is regulated by atleast one transistor.
 50. The method in-claim 49, further comprisingallowing electrical communication with said programmable element throughsaid second pad after packaging said circuit.
 51. The method in claim 50further comprising preventing all electrical communication with saidlatch through said first pad after packaging said circuit.
 52. Themethod in claim 51, further comprising avoiding electrical communicationwith said programmable element through said second pad before packagingsaid circuit.